Ethernet traces on a PCB require controlled impedance, typically 100 Ohms differential for the differential pairs (like Tx+ and Tx-) and 50 Ohms single-ended for individual traces,

Gigabit Ethernet PCB Design

Gigabit Ethernet (1000BASE-T) uses all four twisted pairs of a Cat5e/Cat6 cable simultaneously and bidirectionally, with PAM-5 signaling at 125 MHz per pair. At those frequencies, anything on the PCB between the PHY and the RJ45 connector is no longer “wiring” — it’s a transmission line. Bad layout shows up as link drops, retries, EMI failures, and BER issues that don’t reproduce on a scope.

The whole MDI (Media Dependent Interface) section is the highest-risk part of any board carrying Ethernet. Treat it as analog RF, not as a digital bus.

Signaling cheat sheet

Standard	Pairs used	Symbol rate	Encoding	Bandwidth approx.
10BASE-T	2 (1 Tx, 1 Rx)	10 MBd	Manchester	~10 MHz
100BASE-TX	2 (1 Tx, 1 Rx)	125 MBd	4B/5B + MLT-3	~30 MHz
1000BASE-T	4 (all bidirectional)	125 MBd	PAM-5 + 4D-TCM	~62.5 MHz (3rd harmonic ~190 MHz)
2.5GBASE-T	4 (bidirectional)	200 MBd	PAM-16	~100 MHz
10GBASE-T	4 (bidirectional)	800 MBd	PAM-16 + LDPC	~400 MHz

Even though Gigabit’s fundamental is only ~62 MHz, edges contain energy well into hundreds of MHz. Design for ~500 MHz of signal integrity headroom.

Impedance targets

Net	Target	Tolerance
MDI differential pair (MDI±0…3)	100 Ω differential	±10 %
MDI single-ended (each leg to GND)	50 Ω	±15 %
MII / RMII / RGMII single-ended	50 Ω	±15 %
RGMII differential clock	100 Ω	±10 %
SGMII / 1000BASE-X	100 Ω	±10 %

The 100 Ω differential target is what the cable, the magnetics, the PHY’s MDI buffer, and the receive equalizer all expect. Stray ±20 % from this and the equalizer eats your link margin.

Layout rules — MDI side (PHY ↔ magnetics ↔ RJ45)

These are the rules that matter; everything else is good hygiene.

1. Differential pair geometry

Compute trace width + gap for 100 Ω differential in your specific stackup. Don’t use defaults from another board.
Keep pair geometry constant from PHY pin to magnetics pin. Width/gap changes are reflections.
Edge-coupled microstrip on outer layers is standard. Stripline is better but trades off via complexity.
Use tight intra-pair coupling (gap ≤ trace width is a good starting point).

2. Intra-pair skew (within one pair)

Match the two members of a pair to < 5 mil (1000BASE-T tolerates more, but 5 mil leaves room for 2.5G/10G upgrades).
Match at the source of the mismatch, not at the destination — serpentine right next to the bend that caused the mismatch, not at the connector.
Serpentine segments should be at least 3× trace width long with smooth corners (45° or arcs).

3. Inter-pair skew (between pairs)

Match all four pairs to within ~50 mm (2 in.) of each other for 1000BASE-T. The PHY’s deskew can handle more, but tighter is better.
For 10GBASE-T target tighter, ~25 mm (1 in.).

4. Reference plane

Solid, continuous GND reference under the entire MDI section. No splits, no slots, no signal vias cutting through.
If you must change layers, use a GND stitching via within 100 mil of the signal via on each side.
Don’t route MDI over splits between digital and analog grounds. Either keep it on the digital side and bridge near the magnetics, or treat the whole MDI region as its own “chassis-ground island.”

5. Spacing

3W rule: edge-to-edge spacing between a diff pair and any other signal ≥ 3× the trace width of the pair.
5W rule between MDI pairs and any aggressor (clocks, switching regulators, DDR, USB high-speed).
Keep MDI pairs ≥ 5 mm away from board edges to suppress fringing-field EMI.

6. Length and stubs

Total MDI trace length: typically ≤ 100 mm PHY-to-connector for 1000BASE-T; ≤ 75 mm for 2.5G/10G.
No stubs. No test points. No unterminated bond fingers. A 5 mm stub is a quarter-wavelength antenna at 15 GHz harmonics.
Place the magnetics as close to the RJ45 as physically possible — ideally < 25 mm. Better: use an integrated MagJack.

7. Vias

Minimize via count on MDI pairs. Best layout has zero vias from PHY pin to magnetics pin.
If a via is unavoidable, place vias symmetrically on both legs of the pair and stitch GND nearby.
Use small-drill vias on high-speed pairs (≤ 0.2 mm drill where possible).

The magnetics + RJ45 boundary

The transformer/choke block isolates the PHY side from the cable side both galvanically (1.5 kV+) and in common mode. This boundary has its own ritual:

Bob Smith termination

Each unused (or all four) pair’s center-tap is connected through a 75 Ω resistor to a common chassis-ground node, which is then capacitively coupled (typically 1 nF, 2 kV) to chassis ground. This:

Provides a defined common-mode termination (improves EMI).
Bleeds off ESD safely.
Suppresses cable-driven common-mode currents.

The Bob Smith node should be its own copper pour, isolated from digital GND, joined only via the 1 nF / 2 kV cap. Some designs replace the cap with a screw-down chassis connection.

Magnetics-to-PHY pour (“the moat”)

Cut a clearance “moat” in the GND plane directly under the magnetics, separating the PHY-side GND from the cable-side / chassis-side GND. The transformer is what bridges them; the PCB plane should not.

This is the single highest-impact rule for EMI/ESD compliance. Skipping it is the #1 reason a board passes function but fails radiated emissions.

ESD protection

Place TVS diodes (typical: 6–12 V working, sub-pF capacitance) on the cable side of the magnetics, oriented to the chassis-ground node. Don’t put ESD diodes on the PHY side — they don’t help and add capacitance.

Common-mode chokes

Many MagJacks integrate common-mode chokes. If you use discrete magnetics without CMCs, add a CMC between the PHY and the transformer (typical 350 µH @ 100 MHz, < 0.5 Ω DCR).

PHY-side rules

Separate analog (AVDD) and digital (DVDD) supplies. Bridge them with a ferrite bead (typical 600 Ω @ 100 MHz, low DCR), not a resistor.
Decouple every PHY supply pin with 100 nF as close to the pin as possible; add bulk (4.7–10 µF) per rail nearby.
Crystal/oscillator placed within 25 mm of the PHY, with its own GND guard ring and an unbroken plane underneath. No high-speed signals routed near the crystal.
RBIAS resistor (often 4.99 kΩ, 1 %) — required by most PHYs, must be tight tolerance and physically close.
Reset, strap pins, MDC/MDIO: standard digital; keep MDIO away from MDI but it’s not high-speed.
LED traces: low-speed; route them deliberately to avoid stubbing the MDI pairs at the connector. Buffer LED lines through resistors at the PHY.

Power & EMI

Switching regulators ≥ 25 mm from the MDI region. Orient inductor flux 90° to MDI pairs.
Use shielded inductors on supplies feeding the PHY analog rails.
Chassis ground should be a separate pour, connected to digital GND at exactly one point — typically near the I/O bracket, never under the PHY.
If using a metal panel with screw mounts: bond chassis ground to panel via the screws (low impedance), don’t rely on a “star” wire.

Pre-tape-out checklist

Common failure modes (and where to look)

Symptom	Likely cause
Link drops at 1 Gbps, falls back to 100 Mb/s	Impedance discontinuity, severe inter-pair skew, or marginal magnetics
Works at room temp, fails at 70 °C	Magnetics saturation, or PHY analog rail decoupling marginal
EMI radiated-emissions fail at 100–300 MHz	Missing moat under magnetics, broken GND reference under MDI, or Bob Smith termination missing
ESD strike on cable kills PHY	TVS diodes missing, on wrong side, or no path to chassis
High BER with short cables, OK with long	Echo cancellation problem — usually intra-pair skew or impedance mismatch near PHY
LED noise on RX	LED traces stubbed off MDI net or routed adjacent without buffering
Inconsistent link at boot	RBIAS resistor wrong value/tolerance, or strap pin levels uncertain

Ufuk's Notes

Explorer

Ethernet related electronics notes